By Martin E. Fermann, Almantas Galvanauskas, Gregg Sucha
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This experimental assembly methodology worked well and successfully de-coupled the CMOS/FBAR assembly and the CMOS/board assembly. The oscillator was biased to 200µW per leg for stable startup (400µW total). 6x increase in startup transconductance. In addition, due to the experimental nature of the ISM-band resonators, high variation in resonator motional resistances were expected. 16 shows the steady-state transient oscillator output. 43GHz as expected. The oscillator exhibited a clean Fig. 16.
It is important to note that the finite Q of the CMOS device and pad capacitance must be taken into account, as they also reduce the loaded Q of the oscillator. This optimization led to a maximized value of RL at parallel resonance. The desired voltage swing of the oscillator was 100mV zero-peak. The equation V0 = I1 RL relates the desired voltage swing to the first harmonic component of the drain current of M1 . Thus, since the oscillator is operated in the current-limited regime, the necessary oscillator core bias current is 300µA.
Notice that the phase noise performances of the two oscillators are very was measured similar. 4V. The low supply-pushing figure is due to the 30 2 LOW POWER CMOS DESIGN FOR RADIO FREQUENCIES -90 -100 Phase Noise (dBc/Hz) -110 -120 -130 -140 -150 103 104 105 Frequency Offset (Hz) 106 107 Fig. 12. 2. 2. 2V supply would result in only a 60kHz frequency shift. 3. As expected, the even order harmonics of the differential oscillator are suppressed by the differential architecture. The fourth harmonic was below the noise floor of the spectrum analyzer.
Ultra-Low Power Wireless Technologies for Sensor Networks by Martin E. Fermann, Almantas Galvanauskas, Gregg Sucha